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design note dn 2013 - 01 v1.0 january 2013 ccm pfc boost converter design sam abdel - rahman infineon technologies north america (ifna) corp.
ccm pfc boost converter design 2 design note d n 2013 - 01 v1.0 january 2013 edition 2013 - 0 1 - 0 1 published by infineon technologies north america 27703 emperor blvd, suite 310 , durham, nc 27703 ? infineon technologies north america corp. 2013 all rights reserved. attention please ! the information given in this application note is given as a hint for the implemen - tation of the infineon technologies component only and shall not be regarded as any description or warranty of a certain functionality, condition or quality of the infineon technologies component. the recipient of this application note must verify any function described herein in the real application. infineon technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warran ties of non - infringement of intellectual property rights of any third party) with respect to any and all information given in this application note. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life - support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life - support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. dn 2013 - 01 subjects: ccm pfc boost converter design author: sam abdel - rahman (ifna pmm smd amr pmd 2) we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: [ sam.abdel - rahman@infineon.com ]
ccm pfc boost converter design 3 design note d n 2013 - 01 v1.0 january 2013 table of contents 1 introduction ................................ ................................ ................................ ................................ .................. 4 2 boost topology ................................ ................................ ................................ ................................ ............ 4 3 pfc modes of operation ................................ ................................ ................................ ............................. 5 4 ccm pfc boost design equations ................................ ................................ ................................ ........... 7 5 references ................................ ................................ ................................ ................................ ................. 17
ccm pfc boost converter design 4 design note d n 2013 - 01 v1.0 january 2013 1 introduction power factor correction (pfc) shapes the input current of the power supply to be in synchronization with the mains voltage, in order to maximize the real power drawn from the mains . in a perfect pfc circuit, the input current follows the input voltage as would an equivalent resistor , with no added input current harmonics. this document i s intended to discuss the topology and operation al mode for high power pfc applications (>300w) , and provide detailed design equations with examples. 2 boost topology although a ctive pfc can be achieved b y any basic topology, the boost converter ( figure 2 . 1 ) is the most popular to pology used in pfc applications, for the following reasons: t he line voltage varies from zero to some peak value typically 375v, hence; a step up converter is needed to output a dc bus voltage of 380v or more. for that reason the buck converter is eliminated , and the b uck - boost converter has high switch voltage stress (vin+vo) . moreover, t he boost converter has the filter inductor on the input side, which provides a smooth continuous input current waveform as opposed to the discontinuous input current of a buck or buck - boost topolog y . this continuous input current is much easier to filer, which is a major advantage because any additional f iltering that is needed on the input side of the converter adds cost and reduces the power factor due to capacitive loading of the line . boost key waveforms figure 2 . 1 a c p f c c o n v e r t e r d c / d c c o n v e r t e r l o a d d c b u s v a c a c l d r o v a c c o s + v o - d c b u s s v _ l i _ l i _ s i _ d t = 1 / f d t v i n v i n - v o i _ l m a x i _ l m i n i _ l m a x i _ l m a x i _ l m i n
ccm pfc boost converter design 5 design note d n 2013 - 01 v1.0 january 2013 3 pfc modes of operation the boost converter can operate in three modes: c ontinuous conduction mode (ccm), discontinuous conduction mode ( dcm ), and critical conduction mode (cr c m) . fig. 2 shows modeled wav e forms to illustrate the inductor and input currents in the three operating modes , for the same exact voltage and power conditions . figure 3 . 1 although dcm operation seem s simpler than cr c m, since it may operate in constant frequency operation , dcm has the disadvantage that it has the highest peak current compared to ccm and cr c m, but with no performance advantage compared to cr c m , and one potential disadvantage. for that reason, cr c m is a more common practice than dcm, therefore, this document will exclude the dcm mode. cr c m may be considered a special case of ccm , where operation is controlled to stay at t he boundary between ccm and dcm. crcm usual ly uses constant on - time control; as the line voltage is changing across the 60hz line cycle, the reset time for the boost inductor varies, and the operating frequency will change as well in order while maintain ing boundary mode operation. cr cm dedicated c ontrollers sense the inductor current zero crossing in order to trigger the start of the next switching cycle . when carefully designed, the boost rectifier diode for the crcm pfc is selected not to be ultra - fast, but of medium fast speed, so that the induc tor current not only completely resets to zero but may switch slightly negative. this energy stored in the crcm boost inductor will flyback to ground, achieving zvs turn - on for the boost mosfet under most conditions , particularly at input voltage above 200v, when this will not usually occur for a 400v nominal bulk bus system . t he current ripple (or the peak current) in cr c m is twice the average value, whi ch greatly increases the rms currents and turn off current . but since every switching cycle starts at zero current, and usually with zvs operation, turn on loss is usually eliminated. also, since the boost rectifier diode turns off at zero current as well, reverse recovery losses from q rr a nd noise from switching at high i rrm in the boost diode are eliminated too , another major advantage of cr c m mode . still, on the balance, the high input ripple current and its impact on the input emi filter tend s to eliminate crcm mode for high power designs unless interleaved s tages are used to reduce the input hf current ripple. a high efficiency design can be realized that way, but at substantially higher cost. that discussion is beyond the scope of this design note. c o n t i n u o u s c o n d u c t i o n m o d e ( c c m ) 0 1 10 4 - ? 2 10 4 - ? 3 10 4 - ? 4 10 4 - ? 0 5 10 15 i in t ( ) i l t ( ) t d i s c o n t i n u o u s c o n d u c t i o n m o d e ( d c m ) 0 1 10 4 - ? 2 10 4 - ? 3 10 4 - ? 4 10 4 - ? 0 5 10 15 i in t ( ) i l t ( ) t c r i t i c a l c o n d u c t i o n m o d e ( c r c m ) 0 1 10 4 - ? 2 10 4 - ? 3 10 4 - ? 4 10 4 - ? 0 5 10 15 i in t ( ) i l t ( ) t
ccm pfc boost converter design 6 design note d n 2013 - 01 v1.0 january 2013 the power stage equations and transfer functions for cr c m are the same as ccm. the main differences relate to the current ripple profile and switching frequency, which a ffects rms and switching power losses and filter design . figure 3 . 2 irms normalized by i a /i b ratio in relation to current waveshape cc m operation requires a larger filter inductor compared to cr c m. while the main design concerns for a crcm inductor are low hf core loss, low hf winding loss, and stable value over the operating range (the inductor is essentially part of the timing circuit), the ccm mode inductor takes a different approach. for the ccm mode pfc, t he full load inductor current ripple is typically designed to be 20 - 40 % of the average input current. this has several advantages: (1) p eak current is lower, and the rms current factor with a trapezoidal waveform is reduced compared to a triangular waveform, reducing conduction losses (fig 3.2) . (2) t urn of f losses are lower due to switch off at much lower maximum current. (3) the hf ripple current to be smoothed by the emi filter is much lower in amplitude. on the other side, ccm encounters t urn on losses with the mosfet , which can be exacerbated by the boost rectifier commutation recovery loss due to q rr . for this reason, ultra - fast recovery diodes or silicon carbide schottky diode s with no charge q rr are needed for ccm mode. in conclusion, we can say that for low power applications, the cr c m boost has an advantage in losses and power density . t his advantage may extend to medium power ranges, however at some medium power level the low filtering and the high peak current starts to be come sever e d is advantages. at this point the ccm boost starts being a better choice for high power applications. according to the above , and since this document is intended to support high power pfc applications, the f ollowing are detailed design discussions and design example s for a ccm pfc boost converter .
ccm pfc boost converter design 7 design note d n 2013 - 01 v1.0 january 2013 4 ccm pfc boost design equations the following are design equations for the ccm operated boost, with a design example integrated to further clarify the usage of all equations. the boost converter encounters the maximum current stress and power losses at the minimum line voltage condition ( ); hence , all design equations and power losses will be calculated using the low line voltage condition. table 1 specifications input voltage 85 - 265 vac 60 hz output voltage 39 0 v maximum power steady state 40 0 w switching frequency 10 0 khz inductor current ripple 30% output voltage ripple (2x line frequency) 10 vp - p hold - up time 16.6 ms @ v o.min =350 v figure 4 . 1 block schematic for boost power stage with input rectifier filter inductor the filter inductor value and its peak current are determined based on the specified maximum inductor current ripple . (1)
ccm pfc boost converter design 8 design note d n 2013 - 01 v1.0 january 2013 (2) inductor saturation current, rectifier bridge, mosfet and boost diode , must all be rated at > 7.5a . one practical design would suggest 1 2 a current ratings. (3) (4) off the shelf inductors are available and usable for a first pass design , typ ically with single layer windings and a permeability droop of 30% or less [ ] . in some circumstances it may be desirable to further optimize the inductor configuration, in order to meet requirements for high power factor over a wide line and input current range, and to optimize the inductor size. many of the popular pfc controllers u se what is known as single cycle current loop control, which can provide very good performance provided that the inductor remains in ccm mode operation. at low - line this is no problem, but for operation in the high - line band (176vac to 265vac), the operati ng current will be much lower. if an inductor is used with a nominal stable value of inductance, what works well at low - line results in dcm mode operation for a significant part of the load range at high - line, and poorer power factor and higher emi than necessary. figure 4 . 2 swinging boost inductor example optimized for cmm mode operation over wide range
ccm pfc boost converter design 9 design note d n 2013 - 01 v1.0 january 2013 a swinging choke design can address this, by using a medium permeability core (75 - 125) of core types such as arnold/micrometals sendust and magnetics inc. kool mu, of the right energy capability and designing for full load permeability droop by 75 - 80%, so that with lighter load the inductance swings up. the full details of this technique are beyond the scope of this design note, but it can be facilitated with availab le design tools from core manufacturers [ 2 ]. an example of this with operating current points referenced key line voltage points in one design example is shown in figure 4.2 . rectifier bridge the bridge total power loss is calculated using the average input current flowing through two of the bridge rectifying diodes . (5) recommendation: gbj1006 - bp . using a higher rated current bridge can reduce the forward v f , lowering the total power dissipation at a small incremental cost. this is often a sound strategy, as with modern components, the bridge rectifier usually has the highest total semiconductor loss for the pfc stage. mosfet in order to select the the optimum mosfet, one must understand the mosfet requirements in a ccm boost converter. high voltage mosfets have several families based on different technologies, which each target a specific application, topology or operation. for a boost converter, the following are some major mosfet selec tion considerations : ? low fom s - r on *q g and r on *e oss ? fast turn - on/ off switching , gate plateau near middle of gate drive range (which balances turn - on and turn - off losses) ? low output capacitance c oss for low switching energy, to increase light load efficiency - this relates to the r on *e oss metric . ? switching and conduction losses must be balanced for minimum total loss - this is typically optimiz ed at the low line condition (if best thermals area desired) , where worse case losses and temperature rise o ccur. in other cases, it may be desired to optimize efficiency at a mid load condition, and ensure that the thermal design is adequate for the worst case low - line dissipation. this varies with overall system targets. ? vds rating to handle spikes/overshoots ? low thermal resistance r thjc . package selection must consider the resulting total thermal resistance from junction to ambient, and the worst case surge dissipation - this is typically under low - line cycle skip and recovery into highline while ramping the bu lk voltage back up. ? body diode speed and reverse recovery charge are not important, since body diode never conducts in a boost converter.
ccm pfc boost converter design 10 design note d n 2013 - 01 v1.0 january 2013 the recommended coolmos ? mosfet series for boost applications are the cp series and the c6/e6 /p6 series. cp coolmos ? provides fastest switching ( figure 4 . 3 ) , hence , best performance, but requires careful design in terms of gate driving circuit and pc b layout [3 ] . the c6/e6 series provides a distinct c ost advantage, with easier design, but less performance compare d to cp series. the new (in 2013) p6 series approaches cp performance closely at a better price point, and is recommended for new designs tha t are cost sensitive. [6] according to the aforementioned mosfet selection criteria and to the specification listed in table 1 , the ipw60r 125 cp is selected, and its parameters will be used for the following calculations. the mosfet rms current across the 60hz line cycle can be calcu lated by the following equation; c onsequently the mosfet conduction loss is obtained . (6) (7) for switching losses calculation, the average input current can be used to esti mate losses over the line cycle. the average i nput current is given as: (8) turn - on time and loss : (9) (10) figure 4 . 3
ccm pfc boost converter design 11 design note d n 2013 - 01 v1.0 january 2013 turn - off time and loss : (11) (12) this is the classic format for calculating turn - off time and loss; due to the high q oss of sj mosfets, the c oss acts like a nonlinear capacitive snubber, and actual turn - off losses with fast switching can be up to 50% lower than calculated. the current flow through the drain during turn - off under these conditions is non - dissipative capacitive current, and with fast drive, the channel may be completely turn ed off by the onset of drain voltage rise. output capacitance c oss switching loss : ( 13) gate drive loss : (14) boost diode selection of the boost diode is a major design decision in ccm boost, since the diode is hard commutated at a high current, and reverse recovery can cause significant power loss, noise and current spikes. reverse recovery can be a bottle neck for high switching frequency and high power density power supplies. additionally, at low line, the available diode conduction duty cycle is q uite low, and the forward current quite high in proportion to the average current. for that reason, the first criteria for selecting a diode in ccm boost are fast recovery with low reverse recovery charge , followed by v f operating at high forward current .
ccm pfc boost converter design 12 design note d n 2013 - 01 v1.0 january 2013 since silicon carbide (sic) schottky diodes have capacitive charge (q c ) rather than reverse recovery (q rr ) , their switching loss and recovery time are much lower compared to silicon ultrafast diode, and will show an enhanced performance. moreover, sic diodes allow higher switching frequency designs, hence, higher power density converters. the capacitive charg e for sic diodes are not only low , but also independent on di/dt, current level, and temperature; where si diodes have strong dependency on these conditions, a s shown in figure 4 . 3 . the newer generations of sic diodes are not just schottky devices, but are merged structure diodes known as mps diodes - merged pn/schottky (figure 4.4) . they combine the relatively low v f and capacitive charge characteristics of schottky diodes with the high peak current capability of pn diodes, while avoiding the high junction voltage penalty (typically 2.5 - 3v at room temperature) of a pure pn wide bandgap diode. [ 4 ] the recommended diode for ccm boost applications is the 650v thinq sic generation 5 diodes . sic g5 diodes include infineons leading edge technologies, such as diffusion soldering process and wafer thinning technology. the result is a new family of products showing improved efficiency over all load conditions, coming from both the improved the rmal characteristics and a improved figure of merit (q c x v f ) [5] . figure 4 . 3 figure 4 . 4 : schottky and merged pn/schottky compared
ccm pfc boost converter design 13 design note d n 2013 - 01 v1.0 january 2013 with the high surge current capability of the mps diode, there is some latitude for selection of the boost diode - a simple rule of thumb that works well for a wide input range pfc for good cost/performance tradeoffs is 1a diode rating for 80w of output pow er. for high - line range only applications, or high - line applications with de - rated output power at low - line conditions, this may be adjusted to as much as 150w per 1a of diode rating. in that case, for example, a 600w application in the 176 vac to 255 vac range will only need 4a. but, with the improved q c x v f figure of merit, higher efficiency may be achieved by up to doubling the id rating of the diode, especially for low - line applications where the input current is quite high with a short duty cycle. the higher rated diode will have a much lower v f at the actual operating current, reducing conduction losses. the lower q c means there is no sacrifice of mid range or low range efficiency from using the larger sic diode. note that even when using the mps type sic diode, it is still preferred to use a bulk pre - charge diode as shown earlier in figure 4.1 . this is a low frequency standard diode with high i 2 t rating to support pre - charging the bulk capacitor to the peak of the ac line voltage; this is a high initial surge current stress (which should be limited by a series ntc) that is best avoided for the hf boost rectifier diode. according to the aforementioned diode selection discussion and to the specification listed in table 1 , sic diode idh1 2 g65c5 is selected, and its parameters will be used for the following calculations. th e boost diode carries an average current e qual to the output current. (15) (16) due to current waveforms and duty cycle , the rms value can approach 15% higher under worst case low line conditions, but this requires a much more complex calculation to assess; a simpler form will get you in the ball park. diode conduction loss approximation: (17) diode switching loss , which is carried by the boost mosfet: (18)
ccm pfc boost converter design 14 design note d n 2013 - 01 v1.0 january 2013 output capacitor the output capacitor is sized to meet the hold - up time and voltage ripple requirements , the capacitor is selected to have the larger value of the two equations below . (19) (20) the capacitor rms current across the 60hz line cycle can be calculated by the following equation, consequently the capacitor esr loss is obtained . ( 21) (22) recommendation: 2 parallel eet - uq2s331kf
ccm pfc boost converter design 15 design note d n 2013 - 01 v1.0 january 2013 heatsink the mosfet and diode can have separate heatsinks or share the same one, however, the selection of the heatsink is based on its required thermal resistivity . in case of separate hea tsinks for the diode and mosfet, thermal re sistors are modeled as in figure 4 . 5 . in case of a single heatsink fo r both the diode and the mosfet, thermal re sistors are modeled as in figure 4 . 6 . the maximum heatsink temperature is the minimum outcome of the two equations below once is specifie d , then the heatsink thermal resistance can be calculated. is the thermal resistance from junction to case, this is specified in the mosfet and diode datasheets. is the thermal resistace from case to heatsink, typically low compared to the overall thermal resistance, its value depends on the the interface material, for example, thermal grease and thermal pad. is the thermal resistance from heatsink to ambient , this is specified in the heatsink datasheets , it depends on the heatsink size and design, and is a function of the surroundings, for example, a heatsink could hav e difference values for fo r different airflow conditions. is the heatsink temperature, is the case temperature , is the ambient temperature . is fets total power loss , is diodes total power loss. figure 4 . 5 figure 4 . 6 p fet r thjc . fet r thcs . fet r thjc . diode r thcs . diode r thsa t j . fet t j . diode t s t a t c . fet t c . diode p diode p fet + p diode p fet r thjc . fet r thcs . fet r thsa . fet t j . fet t s . fet t c . fet p diode r thjc . diode r thcs . deiode r thsa . diode t j . diode t s . diode t c . diode
ccm pfc boost converter design 16 design note d n 2013 - 01 v1.0 january 2013 table 2 shows three design examples for the ccm pfc boost converter, for different power levels and switching frequencies . table 2 design example #1 design example #2 design example #3 400w 100khz 700w 80khz 1000w 60khz filter inductor recommendation pfc - 02301 - 00 pfc - 05301 - 00 pfc - 05301 - 00 rectifier bridge gbj1006 - bp gbj1506 - bp gbj2006 - f recommendation gbj1006 - bp gbj1506 - bp gbj2006 - f mosfet ipw60r125cp ipw60r075cp ipw60r045cp boost diode idh12g65c5 idw20g65c5 idw30g65c5 output capacitor recommendation 2 x eet - uq2s331kf 3 x eet - uq2s331kf 3 x eet - uq2s331kf + 1 x eetuq2s391la
ccm pfc boost converter design 17 design note d n 2013 - 01 v1.0 january 2013 5 references [1] precision, inc., vertical mount toroidal inductors. http://www.precision - inc.com/power - factor - correction - inductor - vertical - mount - toroid - p - 691 - l - en.html [2] micrometals arnold powder core inductor desi gn software . http://www.micrometalsarnoldpowdercores.com/software.php [3] f. bjoerk, j. hancock, g. deboy, infineon technologies application note: coolmos cp - how to make most beneficial use of the latest generation of super junction technology devices . february 2007 . http://www.infineon.com/dgdl/aplication+note+coolmos+cp+(+an_coolmos_cp_01_rev.+1.2).p df?folderid=db3a304412b407950112b408e8c90004&fileid=db3a304412b407950112b40ac9a40688 [4] r. rupp, j. hancock, f. bjoerk, m. treu, silicon carbide merged pn/scho ttky diodes for pfc applications, infineon technologies na, v. 1.2, 2008; upon request. [5] product brief , 650v sic thinq!? generation 5 diodes. http://www.infineon.com/dgdl/infineon+ - +product+brief+ - +650v+sic+generation+5+diodes.pdf?folderid=db3a304314dca38901152836c5a412ab&fileid=db3 a3043399628450139b06e16a721d0 [6] coolmos tm selection guide. http://www.infineon.com/dgdl/infineon_coolmos_selection - guide.pdf?folderid= db3a304314dca389011528372fbb12ac&fileid=db3a30432f91014f012f95fc7c243 99d
ccm pfc boost converter design 18 design note d n 2013 - 01 v1.0 january 2013 symbols used in formulas v a c. min : minimum input voltage v o : output voltage v ac.min : minimum input voltage v o : output voltage p o : output power f: switching frequency t: switching time period f line : line frequency l: filter inductor %ripple: inductor current ripple percentage to input current dcr: inductor dc resistance i l.avg : inductor average current across the line cycle i l.pk : inductor peak current p l.cond : inductor conduction loss v f .bridge : br idge diode forward voltage drop p bridge : bridge power loss r on (100c) : mosfet on resistance at 100 o c q gs : mosfet gate - source charge q gd : mosfet gate - drain charge q g : mosfet total gate charge r g : mosfet gate resistance v pl : mosfet gate plateau voltage v th : mosfet gate threshold voltage t on : mosfet switching on time t off : mosfet switching off time e oss : mosfet o utput capacitance switching energy i s.rms : mosfet rms current across the line cycle p s.cond : mosfet conduction loss p s.on : mosfet switching on power loss p s.off : mosfet switching off power loss p s.oss : mosfet o utput capacitance switching loss p s.gate : mosfet gate drive loss i d.avg : boost diode average current v f .diode : boost diode forward voltage drop q rr : boost diode re verse recovery charge p dcond : boost diode conduction loss p d. sw : boost diode switching loss c o : output capacitor esr: output capacitor resistance t hold : hold - up time v o.min : hold up m inimum output voltage ? v o : output voltage ripple i co.rms : output capacitor rms current p co : output capacitor conduction loss

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